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#ifndef DEVICE_DEFS_H
#define DEVICE_DEFS_H

#include <QString>
#include "PlxApi.h"

#define	VENDOR_FZJ					0x1796

#define	DEVICE_ID_0001				0x0001		//	SIS1100
#define	DEVICE_ID_0017				0x0017      // Optisches Interface
#define	DEVICE_ID_0019				0x0019		// PLX9656 / Spartan 3 / OHNE Opto Interface (auch die neue mit USB)
#define	DEVICE_ID_001A				0x001A		// PLX9656 / Spartan 6 / Opto Interface

#define I2C_MAXRETRY            10

#define DEV_REG_I2C_DATA        65

#define DEV_DATASIZE            0x100000		// 1 Mb
#define DEV_DMA_OK              1
#define DEV_READFIFO_OK         1

#define DEV_ERR_INIT_MEMALLO    -1
#define DEV_ERR_INIT_MEMMAP     -2
#define DEV_ERR_INIT_CHO        -3
#define DEV_ERR_INIT_SETP       -4
#define DEV_ERR_EXIT_CHC        -5
#define DEV_ERR_EXITDMA         -6
#define DEV_ERR_BUF_PROP        -7
#define DEV_ERR_MEM_FREE        -8
#define DEV_ERR_MEM_UMAP        -9
#define DMA_ERR_EXITDMA         -10
#define DEV_ERR_READFIFO        -11


#define EEPROM_SERIALNOPOS      0
#define EEPROM_SEGMENTNOPOS     4
//#define MAROC_SPECIALINFOPOS            12
#define EEPROM_SPECIALINFOPOS   1024
#define EEPROM_SPECIALINFOLEN   1024
#define EEPROM_UNINITIALISED    0xFFFFFFFF

#define IDENTIFY_ON             0x00000030
#define IDENTIFY_OFF            0xFFFFFFCF

#define DEV_DONOTCLKRST         0x5

#define HW_MAROC                0x0
#define HW_CCS                  0x1

#define CCS_16BIT               0x0
#define CCS_32BIT               0x1

#define CCS_IDENT               0x0
#define CCS_SERIAL_NR           0x1
#define CCS_HI_WORD             0x2
#define CCS_JTAG_CSR            0x3
#define CCS_JTAG_DATA           0x4	// 32 Bit, use CCC_HI_WORD
#define CCS_SR                  0x5
#define CCS_CR                  0x6
    #define CCS_WRTOEEPROM          0x02
#define CCS_I2C_DATA            0x7
    #define CCS_I2C_ADR_EEPROM      0x50
#define CCS_FUNCTION_0          0x8
#define CCS_FUNCTION_1          0x9
#define CCS_FUNCTION_2          0xA
#define CCS_FUNCTION_3          0xB
#define CCS_FUNCTION_4          0xC
#define CCS_FUNCTION_5          0xD


/*
#define dM_BoardID              500
#define dM_BoardRev             501
#define dM_FirmwareID           502
#define dM_FirmwareRev          503
#define dM_EEPromU32            504
#define dM_EEPromSTR            505
#define dM_SerialNo             506
*/

#define NO_SERIAL               "No Serial"



#define CW_STRWR                0x0100
#define CW_STRRD                0x0200
#define CW_MRST                 0x0400

#define CR_BUSY                 0x0100
#define CR_RD_AV                0x0200
#define CR_WD_AV                0x0400
#define CR_WD_FULL              0x0800
#define CR_NACK0                0x1000
#define CR_NACK1                0x2000


#define I2C_ERR_NOADRACK        -2
#define I2C_ERR_NODATAACK       -3


#define DEV_CHECK               true
#define DEV_NO_CHECK            false


#define MAX_NO_OF_PCI_DEVICES       8

#define CR_RESET				0x00001L        // general reset
#define CR_REM_RESET			0x10000L    	// send reset request to remote

#define THW_SO_HD               0x00000001L		// temp prot, start on writing header
#define THW_SO_AD               0x00000002L		// temp prot, start on address
#define THW_SO_DA               0x00000004L		// temp prot, start on writing data
#define HW_WR                   0x00000400L		// header word, write request
#define HW_AM                   0x00000800L		// VME address modifier
#define HW_A64                  0x00001000L		// 64 Bit address
#define HW_BT                   0x00002000L		// Blocktransfer
#define HW_FIFO                 0x00004000L		// FIFO mode (no address increment)
#define HW_EOT                  0x00008000L		// for Blocktransfers
#define HW_R_BUS                0x00010000L		// remote bus space
#define HW_R_DMD                0x00020000L		// demand remote space
#define HW_L_PIPE               0x00400000L		// read pipe local space
#define HW_L_DMD                0x00800000L		// demand local space
#define HW_BE                   0x0F000000L		// byte enable
#define HW_BE0011               0x03000000L




#define	CPE_INITOPTOLINK		100
#define CPE_GETVERSION          101
#define CPE_GETSERIAL           102
#define CPE_READLINKMEMREG      103
#define CPE_WRITELINKMEMREG     104
#define CPE_READLINKMEM         105
#define CPE_WRITELINKMEM        106
#define CPE_READBASEREG         107
#define CPE_WRITEBASEREG        108
#define CPE_READEXTBASEREG      109
#define CPE_WRITEEXTBASEREG     110


#define C_MNDIAL    0x01	// mode no dial
#define J_SLOW		0x02
#define J_IRUP		0x04	// IR update by Idle state (CONFIG instruction)
#define J_OLD1		0x08	// insert cycle before read
#define J_OLD2		0x10
#define J_PLOAD     0x20	// parallel load
#define J_VQ44		0x40	// XC18V01 package
#define J_2SERNR	0x80	// two serial numbers


#define C_MAILEXT		192
#define C_SP1_SEL		64		// # of SPACE1 selectors
#define CT_SP1_SEL      4		// for this test program

typedef struct {
    quint32	hdr;
    quint32	am;
    quint32	ad;
    quint32	ad_h;
} BUS_DESCR;

typedef struct {
    quint32	ident;		//000

    quint32	sr;			// 	status register
#define MAROC_SR_PROT_L_ERR			0x00008000L
//#define MAROC_SR_DATAAVAIL			0x00000010L
//#define MAROC_SR_D_CNT_CLR			0x01000000L


    quint32	cr;			// 	control register (interrupt enable bits)
    quint32	semaphore;
    quint32	doorbell;	//010 only remote, access to L2PDBELL for local
    quint32	res0[3];
    quint32	mailbox[8];	//020 only remote, access to MBOX[0-7] for local
    quint32	res1[16];

    quint32	t_hdr;		//080
    quint32	t_am;
    quint32	t_ad;
    quint32	t_ad_h;
    quint32	t_da;			//090
    quint32	t_da_h;
    quint32	prot_err_nw;

    quint32	tc_hdr;
    quint32	tc_da;		//0A0
    quint32	res3;			//		tc_da_h

    quint32	balance;		// 	counter for request(up)/confirmation(down)
    quint32	prot_err;	// 	first protocol error (read and clear)

    quint32	d0_bc;		//0B0 dma0 demand byte count (for DAQ)
    quint32	d0_bc_adr;	//		pci address to buffer for byte counts
    quint32	d0_bc_len;	//		buffer length

    quint32	d_hdr;		//		block transfer or pipelined read
    quint32	d_am;			//0C0
    quint32	d_ad;
    quint32	d_ad_h;
    quint32	d_bc;
    quint32	res4[2];		//0D0

    quint32	rd_pipe_adr;//		pci address to buffer for pipelined read
    quint32	rd_pipe_len;//		length of the buffer
    quint32	res5[2];		//0E0

    quint32	tp_special;	//		transparent mode, write special word
    quint32	tp_data;		//		transparent mode, write data word
    quint32	opt_csr;		//0F0	control/status for optical interface, pigy back
    quint32	jtag_csr;	//		JTAG control/status
    quint32	jtag_data;	//		JTAG data
    quint32	res6;

    quint32	mailext[C_MAILEXT];//100
//	0x400
    BUS_DESCR	bus_descr[C_SP1_SEL];	// descriptor for direct bus access, space1
// 0x800
} DEV_REGS_SIS1100;


typedef struct {
    quint32	dmamode;
    quint32	dmapadr;
    quint32	dmaladr;
    quint32	dmasize;
    quint32	dmadpr;
} PLX_DMA;					// 14


typedef struct {			//		complete register set
    quint32	las0rr;		// 00
    quint32	las0ba;
    quint32	marbr;		// 08
    quint8	bigend;             // char
    quint8	lmisc1;             // char
    quint8	prot_area;          // char
    quint8	lmisc2;		//		// char         PCI9656
    quint32	eromrr;		// 10
    quint32	eromba;
    quint32	lbrd0;		// 18
    quint32	dmrr;
    quint32	dmlbam;		// 20
    quint32	dmlbai;
    quint32	dmpbam;
    quint32	dmcfga;
    quint32	opqis;		// 30
    quint32	opqim;
    quint32	space1[2];	// 38
    quint32	mbox[8];		// 40
#define iqp		mbox[0]
#define oqp		mbox[1]

    quint32	p2ldbell;	// 60
    quint32	l2pdbell;
    quint32	intcsr;
#define PLX_INT_ENA		0x000100L
#define PLX_IDOOR_ENA	0x000200L
#define PLX_ILOC_ENA		0x000800L
#define PLX_IDOOR_ACT	0x002000L
#define PLX_ILOC_ACT		0x008000L
#define PLX_IDMA0_ENA	0x040000L
#define PLX_IDMA1_ENA	0x080000L
#define PLX_IDMA0_ACT	0x200000L
#define PLX_IDMA1_ACT	0x400000L

#define PLX_REG_EEPROM        0x6F
    quint32	cntrl;
#define EESK	0x01000000L
#define EECS	0x02000000L
#define EEDO	0x04000000L
#define EEDI	0x08000000L
#define EEPR	0x10000000L

    quint32	pcihidr;		// 70
    quint32	pcihrev;
    quint32	space2[2];
    PLX_DMA	dma[2];		// 80
    quint8	dmacsr[2];	// A8       // char
#define D_ENABLE	0x01
#define D_START	0x02
#define D_CLR_INT	0x08

    quint16	space3;             //short
    quint32	dmaarb;		// AC same as marbr
    quint32	dmathr;		// B0
    quint32	dmadac[2];
    quint32	space4;
    quint32	mqcr;			// C0
    quint32	qbar;
    quint32	ifhpr;
    quint32	iftpr;
    quint32	iphpr;		// D0
    quint32	iptpr;
    quint32	ofhpr;
    quint32	oftpr;
    quint32	ophpr;		// E0
    quint32	optpr;
    quint32	qsr;
    quint32	space5;
    quint32	las1rr;		// F0
    quint32	las1ba;
    quint32	lbrd1;
    quint32	dmdac;
    quint32	pciarb;		//100	PCI9656
    quint32	pabtadr;
} PLX_REGS_9656;


/*
typedef struct {			//		single register !!!! only for finding the hardware type
    quint32	version;		// 00   Bit 31-24 : Firmware Rev.
                            //      Bit 23-16 : Firmware ID
                            //      Bit 15-08 : Board Rev.
                            //      Bit 07-00 : Board ID
    quint32	serial;         // 01   32 Bit Serial Number
} DEV_REGS_VERSION;
*/



#define BOARDID_UNKNOWN             0x00
#define BOARDID_PSF1100             0x01
#define BOARDID_IGNORE              0xFF

#define LINKID_UNKNOWN              0x00
#define LINKID_MAROC                0x12
#define LINKID_MAROCTEST            0x11
#define LINKID_MAROC_OLD            0x04
#define LINKID_CONCENTRATOR         0x10


typedef struct {
#define FIRMWAREREV_UNKNOWN         0x00
#define DEV_MASK_FIRMWAREREV        0xFF000000
#define DEV_SHIFT_FIRMWAREREV       24
    quint8  FirmwareRev;

#define FIRMWAREID_UNKNOWN          0x00
#define DEV_MASK_FIRMWAREID         0x00FF0000
#define DEV_SHIFT_FIRMWAREID        16
    quint8  FirmwareID;

#define BOARDREV_UNKNOWN            0x00
#define DEV_MASK_BOARDREV           0x0000FF00
#define DEV_SHIFT_BOARDREV          8
    quint8  BoardRev;

    quint8  BoardID;

#define SERIAL_UNKNOWN              0x00000000
    quint32 SerialNo;

    bool    Error;
} DEV_LINK_INFO;



typedef struct {
#define IDENT_UNKNOWN               0xFFFFFFFF
    quint32 Ident;

#define FIRMWAREREV_UNKNOWN         0x00
#define DEV_MASK_FIRMWAREREV        0xFF000000
#define DEV_SHIFT_FIRMWAREREV       24
    quint8  FirmwareRev;

#define FIRMWAREID_UNKNOWN          0x00
#define DEV_MASK_FIRMWAREID         0x00FF0000
#define DEV_SHIFT_FIRMWAREID        16
    quint8  FirmwareID;

#define BOARDREV_UNKNOWN            0x00
#define DEV_MASK_BOARDREV           0x0000FF00
#define DEV_SHIFT_BOARDREV          8
    quint8  BoardRev;

    quint8  BoardID;

//#define SERIAL_UNKNOWN              0x00000000
    quint32 SerialNo;

//#define SEGMENT_UNKNOWN             0xFFFFFFFF
    quint32 SegmentNo;

    bool    Error;
} DEV_BASE_INFO;


#define DEV_MASK_BOARDID            0x000000FF
#define DEV_SHIFT_BOARDID           0

#define DEV_SYNC_BASE               0x0002
#define DEV_SYNC_RESET              0x00
#define DEV_SYNC_STOP               0x02
#define DEV_SYNC_START              0x04
#define DEV_SYNC_STARTRESET         0x06



// Standard Register aller Kartentypen
#define DEV_REG_IDENT               0
#define DEV_REG_SERIAL              1
#define DEV_REG_JTAG_CSR            2
#define DEV_REG_JTAG_DATA           3
#define DEV_REG_STATUS              4
#define DEV_REG_CONTROL             5



typedef struct {
//    bool        Open;
    bool        Error;
    quint8      Bus;
    quint8      Slot;
    quint16     DeviceId;
    quint32     DMABufferSize;
} DEV_PLX_INFO;





#define MAROC_MAXMAROCCHANNELS               64
#define	MAROC_MAX_ADCMEM                     256


typedef struct {
#define	MAROC_SEQMEMOFF			2048
    quint32		seqmem[2048];					// gibt es nicht mehr, nur noch als Platzhalter
#define	MAROC_ADCMEMOFF			4096
    quint32		adcmem[MAROC_MAX_ADCMEM];
} DEV_MAROC_MEM;

typedef struct {
    quint32		version;			//00
    quint32		sr;                 //04 Status Register
#define DBELL_PFULL		0x00000004L
#define DBELL_DATARDY	0x00000002L
#define DBELL_BLOCK		0x00000001L

    quint32		cr;                 //08 Control Register, 8 bit
#define SCR_DDTX		0x01        // direct data transfer
#define SCR_SCAN		0x02        // scan LVD front bus
#define SCR_EV_DBELL	0x04        // single event doorbell
#define SCR_LED0		0x08        // untere linke LED
#define SCR_LED1		0x10        // untere rechte LED

    quint32		res0C;              //0C ist in SIS1100 fuer semaphore reserviert

    quint32		dd_counter;         //10
    quint32		dd_blocksz;         //14
    quint32		jtag_csr;           //18 JTAG control/status
    quint32		jtag_data;          //1C JTAG data

    quint32		timer;              //20
    quint32		r24;				//24
    quint32		r28;				//28
    quint32		r2C;				//2C

    quint32		r30;				//30
    quint32		r34;				//34
    quint32		r38;				//38
    quint32		r3C;				//3c

    quint32		r40;				//40
    quint32		r44;				//44
    quint32		r48;				//48
    quint32		r4C;				//4c

    quint32		r50;				//50
    quint32		r54;				//54
    quint32		r58;				//58
    quint32		r5C;				//5c

    quint32		r60;				//60
    quint32		r64;				//64
    quint32		r68;				//68
    quint32		r6C;				//6c

    quint32		r70;				//70
    quint32		r74;				//74
    quint32		r78;				//78
    quint32		r7C;				//7c

} DEV_MAROC_MEMREGS;



typedef struct {
    bool                _Open;

    quint32             Ident;
    int                 _DeviceNo;
//    QList<quint32>      _RegList;

    quint32             Chip;
    PLX_DEVICE_KEY		key;
    PLX_DEVICE_OBJECT	pdo;
    PLX_PCI_BAR_PROP	devprop[6];
//    HANDLE              plx_hDevice;
    PLX_UINT_PTR        plx_Va[6];
    //quint32             plx_Va[6];

    DEV_PLX_INFO        PlxInfo;
    DEV_LINK_INFO       LinkInfo;
    DEV_BASE_INFO       BaseInfo;
    volatile    PLX_REGS_9656           *plx9656_regs;
    //    volatile    quint32                 *reg_plx9656;
    //#define MAX_PLXREGS         256
    //#define REG_PLX_VERSION         0
    //#define REG_PLX_SERIALNO        1

    QList<quint32>      _SisRegList;
    //    volatile    DEV_REGS_SIS1100        *sisregs;
    volatile    quint32                 *sisregs;
#define MAX_BASEREGS                0x200
#define SIS_REG_IDENT               0x000
#define SIS_REG_SR                  0x001
#define SIS_REG_CR                  0x002
#define SIS_REG_BALANCE             0x02A
#define SIS_REG_PROT_ERR            0x02B
#define SIS_REG_BUSDESC_0_HDR       0x100
#define SIS_REG_BUSDESC_0_AD        0x102

#define SIS_REG_T_HDR               0x020
#define SIS_REG_T_AD                0x022
#define SIS_REG_T_DA                0x024
#define SIS_REG_D0_BC               0x02C
#define SIS_REG_D0_BC_ADR           0x02D
#define SIS_REG_D0_BC_LEN           0x02E
#define SIS_REG_OPT_CSR             0x03C
    #define SIS_REG_OPT_CLKRST        0xA0000000

#define SIS_REG_JTAG_CSR            0x03D
#define SIS_REG_JTAG_DATA           0x03E


//    volatile    quint32                 *version_reg;
#define REG_VERSION_VERSION         0
#define REG_VERSION_SERIALNO        1

    volatile    quint32                 *memregs;
#define MAX_LINKREGS        0x400

//    volatile    quint32                 *mem;
//#define MAX_LINKMEM         8192

//    volatile    quint32                 *reg_link;
#define MAX_EXTBASEREGS     256

    quint32             DeviceData[DEV_DATASIZE];

    PLX_PHYSICAL_MEM	Dma_PlxDriverBufferInfo;
    bool                Dma_PlxDriverBufferInfo_ok;
    PLX_DMA_PROP		Dma_Desc;
    PLX_DMA_PARAMS		Dma_Data;
} DEVICE_DATA;



#endif // DEVICE_DEFS_H