dlgjtag_jdef.h 4.67 KB
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#ifndef DLGJTAG_JDEF_H
#define DLGJTAG_JDEF_H



//
//-------------------------------
//			JTAG definitions
//-------------------------------
//
// instruction opcodes und register length stehen in
//		\Xilinx\xc18v00\data\xc18v0?.bsd
//		\Xilinx\spartan2\data\xc2s*.bsd
//		\Xilinx\virtex\data\xcv400.bsd
//		\Xilinx\virtex2\data\xc2v?000.bsd
//
#define C_JTG_DEVS	8

#define TDI			0x001
#define TMS			0x002
#define TCK			0x004
#define TDO			0x008
#define RUNTST		0x010
#define JT_ENA		0x100
#define JT_AUTO     0x200
#define JT_SLOW     0x400
//
// folgende Instruction gelten nur fuer xc18v00
//
#define SERASE		0x0A	// Globally refines the programmed values in the array
#define FVFY3		0xE2
#define FVFY6		0xE6
#define ISPEN		0xE8
#define FPGM		0xEA	// Programs specific bit values at specified addresses
#define FADDR		0xEB	// Sets the PROM array address register
#define FERASE		0xEC	// Erases a specified program memory block
#define FDATA0		0xED	// Accesses the array word-line register ?
#define CONFIG		0xEE
#define NORMRST     0xF0	// CONLD, Exits ISP Mode ?
#define FDATA3		0xF3	// 6
#define FVFY1		0xF8	// Reads the fuse values at specified addresses
#define USERCODE	0xFD
#define IDCODE		0xFE

#define XSC_DATA_RDPT		0x0004
#define XSC_DATA_UC			0x0006
#define XSC_DATA_DONE		0x0009
#define XSC_DATA_CCB		0x000C
#define XSC_BLANK_CHECK		0x000D
#define XSC_DATA_SUCR		0x000E
#define XSC_OP_STATUS		0x00E3
#define ISC_PROGRAM			0x00EA	// FPGM
#define ISC_ADDRESS_SHIFT	0x00EB	// FADDR
#define ISC_ERASE			0x00EC	// FERASE
#define ISC_DATA_SHIFT		0x00ED	// FDATA0
#define XSC_READ			0x00EF
#define CONLD				0x00F0	// NORMST
#define XSC_DATA_BTC		0x00F2
#define XSC_CLEAR_STATUS	0x00F4
#define XSC_DATA_WRPT		0x00F7
#define XSC_UNLOCK			0xAA55

#define V5_IDCODE			0x3C9
#define V5_JPROGRAM         0x3CB
#define V5_CFG_IN			0x3C5
#define V5_ISC_ENABLE       0x3D0
#define V5_ISC_PROGRAM      0x3D1
#define V5_ISC_DISABLE      0x3D6
#define V5_JSTART			0x3CC
#define V5_USER3			0x3E2

#define BYPASS          0xFFFF



#define  JTAG_PROGRAM      0
#define  JTAG_VERIFY       1
#define  JTAG_READSAVE     2

#define  JTAG_FAST         0
#define  JTAG_SLOW         1

#define	MAXPATH	1000


//
//--------------------------- display_errcode --------------------------------
//
#define CEN_PROMPT		-2		// display no command menu, only prompt
#define CE_MENU			1
#define CE_PROMPT			2		// display no command menu, only prompt
#define CE_FORMAT			4
#define CE_FATAL			5

#define C_BUF	0x1000
typedef struct {
    uchar	mcs_buf[0x1000];
    uchar	dr_tdi[0x400000];	// DR values
    uchar	dr_itdo[0x400000];
    uchar	dr_tdo[0x1000];
    uchar	dr_mask[0x1000];
} JTBUF;







// -------------------------- Configuration Buffer --------------------------
//
typedef struct {
    char			jtag_menu;
    char			mode;
#define C_MNDIAL	0x01	// mode no dial
#define J_SLOW		0x02
#define J_IRUP		0x04	// IR update by Idle state (CONFIG instruction)
#define J_OLD1		0x08	// insert cycle before read
#define J_OLD2		0x10
#define J_PLOAD     0x20	// parallel load
#define J_VQ44		0x40	// XC18V01 package
#define J_2SERNR	0x80	// two serial numbers

    uchar		rt_speed;
    uchar		jtag_dev;
    quint16		jtag_ctrl;
    quint16		jtag_instr;
    quint16		jtag_dlen;
    quint32		jtag_data;

#define C_JT_NM		5
    char		jtag_file[C_JT_NM][80];
    char		jtag_svf_file[C_JT_NM][80];
} JT_CONF;

typedef struct {
    quint32     id;
    QString 	name;
    quint32		fam;
#define FM_XC18V        0x01
#define FM_XCF_S        0x02
#define FM_XCF_08P      0x04
#define FM_XCF_16P      0x08
#define FM_XCF_32P      0x10
#define FM_XCF_P        (FM_XCF_32P|FM_XCF_16P|FM_XCF_08P)

#define FM_FLASH        0x001F  // Flag, welches alle gültigen Bits für die Flash Erkennung enthält

#define FM_PBI			0x20


    quint32		ir_len;
    quint32		data0;		// number of bytes, beachte Groesse dr_tdi[]
    quint32    	size0;
    quint32  	erasetest;
} DEV_DESC;



typedef struct {
    quint32		num_devs;
    quint32 	select;
    quint32		state;
 #define JT_UNKNOWN	-1		// unknown device (corrupted JTAG chain)
 #define JT_RESET		0		// state is RESET
 #define JT_IDLE		1		// state is RTI (RUN-TEST/IDLE)
 #define JT_DR_SHIFT	2		// state is SHIFT-DR => Jtag_Rd_Data()

    struct {
        quint32    	idcode;
        DEV_DESC	*ddesc;	// device descriptor
    } devs[C_JTG_DEVS];
    quint32     PromNr[JTAG_MAX_PROMS];
    quint32     PromAnz;
} JTAG_TAB;

//#pragma pack(1)
typedef struct {
    uchar	bc;
    quint16	addr;
    uchar	type;
    uchar	data[0x20+1];
} MCS_RECORD;
//#pragma pack()



#endif // DLGJTAG_JDEF_H